CMOS circuits in the past including inverter circuits, NAND circuits, etc. include field effect transistors, each having a field effect transistor of p-channel type and a field effect transistor of n-channel type which are arranged side by side. Attempts have been made to scale down the layout of components, thereby increasing the gate density and reducing the power consumption. However, the scaling itself is becoming difficult as the technique of fabrication becomes more sophisticated and the manufacturing cost has been remarkably increasing.
One of the next-generation devices with low power consumption is the tunnel field effect transistor (TFET). The development of TFET has attracted attention to the two-dimensional material (2D material) such as Transition Metal DiChalcogenides (TMDC). An example of the TFET is disclosed in Japanese Patent Laid-open No. 2015-090984. The semiconductor element disclosed in the Japanese Published Unexamined Patent Application includes a semiconductor layer containing a two-dimensional substance and at least one non-semiconductor layer on at least one surface of the semiconductor layer, with the two-dimensional substance including a first two-dimensional substance containing a first metal chalcogenide substance and a second two-dimensional substance connecting to the side of the first two-dimensional substance and containing a second metal chalcogenide substance, the first two-dimensional substance and the second two-dimensional substance being chemically bonded together.